1. Field of the Invention
The present invention relates to a DC offset cancellation apparatus, and more particularly to a DC offset cancellation apparatus in a time division duplexing mode direct conversion receiver.
2. Description of the Related Art
In general, a receiver of a communication apparatus generates DC offset. Such DC offset distorts an amplitude of a received signal so that an undesirable signal is received. At this time, if a signal received in the receiver is large, distortion of the signal may cause a receiving function of the receiver to stop. Also, such amplitude distortion causes the receiver to have an erroneous RSSI (Received Signal Strength Indicator) so that the amplitude distortion also exerts an influence when controlling an output of a transmitter. As a result, it is necessary to cancel the DC offset of the receiver.
Usually, the DC offset of the receiver is canceled by using AC-coupling or by repeatedly performing charge or discharge in TDMA (Time Division Multiple Access). In the former, i.e. using the AC-coupling, when canceling the DC offset by means of a high-pass filter, it is possible to lose near-DC information. It is known that the latter, i.e. repeatedly performing charge or discharge in TDMA, is not suitable for canceling the DC offset generated by re-radiation through an antenna in an active mode.
Also, a conventional offset cancellation technique is realized by using a mean value, a measurement unit, an auto gain controller (AGC) value, an integrator and so forth, in such a manner that the offset cancellation can be used for the active mode regardless of either a Frequency Division Duplexing (FDD) mode (i.e., CDMA 2000-Qualcomm) or a Time Division Duplexing (TDD) mode. However, this conventional offset cancellation technique increases a chip area and power consumption because it requires use of such various digital elements.
Also, conventional DC offset cancellation techniques in a digital domain cannot deal with re-radiation, which randomly varies depending on time (the number of clock cycles) required for calculating the mean value. Furthermore, if the time for calculating the mean value is extended, the conventional DC offset cancellation technique can lose a real-time characteristic of detection and correction. Conventionally, communication standards are not based on such hardware constraints. In addition, an FDD system must perform an additional calculation for obtaining an AGC value due to dispersion of AGC gain parameters in an analog/digital domain. Also, FDD systems require a complex interface with respect to a CPU (Central Process Unit) while performing a gain control process.
Meanwhile, since an offset cancellation unit used for a conventional TDD mode is required to detect preamble data, it is unnecessary to perform an additional calculation for extracting dispersed AGC parameters. However, since such an offset cancellation unit creates time delay, the offset cancellation unit loses its real-time characteristic.